The present invention relates to semiconductor storage devices.
Reference characters representing terminal names also denote the names of leads and signals and, in the case of a power supply, its voltage value so long as they are not especially noted otherwise.
A conventional dynamic random access memory (DRAM) has a structure shown in FIG. 13.
A memory cell MC of one transistor and one capacitor is disposed at each of cross points where word lines W1-W4 and data lines D1-D2 cross.
RA1 and RA2 each denote a sense amplifier which reads outs and rewrites a signal from and into the memory cell and which is driven by common sources PN and PP.
A common source signal is generated by a PC0 which short-circuits and precharges common sources PP and PN to a voltage level HV, a pMOS transistor DP1 which charges the common source PP to a high voltage VD and an nMOS transistor DN1 which charges the common source PN to a low voltage VS.
The drive signal for the DP1 is identified by RP while the drive signal for the DN1 is identified by RN.
PC1 and PC2 each denote a circuit which short-circuits and precharges the pair of data lines to HV.
DA1 and DA2 each denote a circuit which transfers a signal appearing on the pair of data lines to the later circuit, and also which transfers from the later stage a signal to be written into a memory cell through the pair of data lines.
A pair of I/O and I/O are inputs/outputs for DA1 and DA2, which control the transfer of a signal from the pair of data lines to a later stage circuit using YS1 and YS2.
In such a DRAM, the electric charges stored in a memory cell would normally become lost as various leak currents.
Therefore, the same data must be rewritten into the memory cell at constant intervals of time.
This operation is called a refreshing operation, which will be described with reference to FIG. 14.
A clock signal CK used for control of this operation is provided as an external clock signal such as RAS or generated internally by an oscillator.
In an initial state, the CK is at low level, RP is at high level, and RN is at low level. Therefore, the DP1 and DN1 are off.
Since FP is at high level VD, the pair of data lines and common sources PP and PN are short-circuited and hence are at a voltage level HV.
YS1 and YS2 are at low level and DA1 and DA2 are off.
In the refreshing operation, YS1 and YS2 are at low level throughout.
The word line is at VS.
If CK changes from low level to high level, first, FP changes to low level VS.
As a result, the pair of data lines and common sources PN and PP float at a level of HV. Thus, word line W1 is selected to change to high level VCH.
Therefore, a small voltage difference which corresponds to data from a memory cell occurs between the pair of data lines D1 and D1.
RP and RN are then inverted.
Therefore, DN1 is turned on and common source PN is discharged toward VS. DP1 is turned on so that common source PP is charged toward YD. Thus, sense amplifiers RA1 and RA2 operate, so that the small voltage signal difference is amplified on the pair of data lines to a large amplitude VD-VS. When amplification ends, the word line changes to low level VS, RP and RN are inverted, and DP1 and DN1 are turned off.
Thereafter, FP changes to high level VD and the pair of data lines and common sources PN and PP are short-circuited to HV. This is the refreshing operation in the conventional DRAM.
When data in the DRAM is to be held by backup of a battery, a so-called standby source current is mainly determined by the refreshing current.
How to reduce the refreshing current is important to suppress the consumed current.
The memory cells are sequentially refreshed in the standby state.
The refreshing current is composed of the operating current in the refreshing control circuit and the data line charge and discharge currents.
In order to reduce the current flowing through the refreshing control circuit, a study of minimizing the number of elements of the circuits has been made. A Japanese Patent Publication JP-60-45997 discloses suppression of the charge and discharge currents on the data lines by reducing the voltage supplied to the refreshing control circuit in a standby state or increasing the refreshing period.
However, this publication only discloses how to suppress the consumed current from the side of the power supply and does not at all refer to an effective use of the current in the circuit.